1. Field of Invention
The present invention generally relates to a semiconductor package, and more particularly, to a substrate for a semiconductor package which can minimize the occurrence of a crack in a circuit trace even when an external stress is applied, and a semiconductor package having the same.
2. Description of the Related Art
A BGA (ball grid array) package and an FBGA (fine ball grid array) package are representative examples of Chip scale semiconductor packages. These packages use ball type leads, that is, conductive solder balls, as terminals for electrically coupling a semiconductor chip with an outside. The conductive solder balls are formed in such a manner that patterns of a conductive substance are attached to the back side of a printed circuit board in a matrix type to define an array. The FBGA package as a kind of the BGA package adopts solder balls which are relatively small when compared to those of the BGA package and are arranged with a narrow spacing.
Unlike a conventional plastic package, the BGA package uses a printed circuit board (PCB) instead of a lead frame. Since the printed circuit board can provide an entire surface facing away from a surface to which a semiconductor chip is attached, as a region for disposing solder balls, advantages are provided in terms of mounting density with respect to a mother board.
As the printed circuit board is widely used as various kinds of boards for electronic systems, the printed circuit board plays an important role along with a semiconductor device in configuring the electronic systems.
Meanwhile, as integrated circuits rapidly trend toward a high speed operation and a high degree of integration, the number of input/output terminals has increased when packaging a semiconductor device. Due to this fact, the number of balls of the BGA package has increased, and the density of circuit traces of the printed circuit board which is used as a packaging substrate has continuously increased.
That is to say, with development of a semiconductor design technology and a semiconductor device technology, the operation speed of an apparatus is being increased and an operation voltage is being lowered. In this case, a spacing between circuit traces should be increased to prevent short-circuiting of the circuit traces of the printed circuit board, and the width of the circuit traces should be decreased to improve a characteristic impedance. However, as the width of the circuit traces is decreased, the mechanical strength of the circuit traces deteriorates. Thus, in the case where physical deformation occurs in a semiconductor package, a problem may be caused in that the circuit traces are apt to snap.